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authorLiam <byteslice@airmail.cc>2022-03-16 16:05:04 +0100
committerLiam <byteslice@airmail.cc>2022-03-16 16:05:04 +0100
commit1415542f73fe013a010f03937697a1d22653b95c (patch)
treeaabfb327fca6cb0dcc5bb2d66862f60565965396 /src/shader_recompiler/frontend
parentshader: add support for const buffer indirect addressing (diff)
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Diffstat (limited to 'src/shader_recompiler/frontend')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp14
1 files changed, 12 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
index 2300088e3..8007a4d46 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
@@ -11,10 +11,20 @@ namespace Shader::Maxwell {
using namespace LDC;
namespace {
std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index,
- const IR::U32& reg, const IR::U32& imm) {
+ const IR::U32& reg, const IR::U32& imm_offset) {
switch (mode) {
case Mode::Default:
- return {imm_index, ir.IAdd(reg, imm)};
+ return {imm_index, ir.IAdd(reg, imm_offset)};
+ case Mode::IS: {
+ // Segmented addressing mode
+ // Ra+imm_offset points into a flat mapping of const buffer
+ // address space
+ const IR::U32 address{ir.IAdd(reg, imm_offset)};
+ const IR::U32 index{ir.BitFieldExtract(address, ir.Imm32(16), ir.Imm32(16))};
+ const IR::U32 offset{ir.BitFieldExtract(address, ir.Imm32(0), ir.Imm32(16))};
+
+ return {ir.IAdd(index, imm_index), offset};
+ }
default:
break;
}