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author | bunnei <bunneidev@gmail.com> | 2018-09-26 22:10:55 +0200 |
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committer | GitHub <noreply@github.com> | 2018-09-26 22:10:55 +0200 |
commit | cc866d138468f648033dcd1ae4a54ed0f6e78aea (patch) | |
tree | f750182f357fe6648a314187adfa4a9bec73197e /src/video_core/engines/maxwell_compute.cpp | |
parent | Merge pull request #1401 from lioncash/vfs (diff) | |
parent | video_core: Add asserts for CS, TFB and alpha testing (diff) | |
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Diffstat (limited to 'src/video_core/engines/maxwell_compute.cpp')
-rw-r--r-- | src/video_core/engines/maxwell_compute.cpp | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp index e4e5f9e5e..59e28b22d 100644 --- a/src/video_core/engines/maxwell_compute.cpp +++ b/src/video_core/engines/maxwell_compute.cpp @@ -2,12 +2,29 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. +#include "common/logging/log.h" +#include "core/core.h" #include "video_core/engines/maxwell_compute.h" namespace Tegra { namespace Engines { -void MaxwellCompute::WriteReg(u32 method, u32 value) {} +void MaxwellCompute::WriteReg(u32 method, u32 value) { + ASSERT_MSG(method < Regs::NUM_REGS, + "Invalid MaxwellCompute register, increase the size of the Regs structure"); + + regs.reg_array[method] = value; + + switch (method) { + case MAXWELL_COMPUTE_REG_INDEX(compute): { + LOG_CRITICAL(HW_GPU, "Compute shaders are not implemented"); + UNREACHABLE(); + break; + } + default: + break; + } +} } // namespace Engines } // namespace Tegra |