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author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-08-28 21:09:33 +0200 |
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committer | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-08-28 21:09:33 +0200 |
commit | e3534700d79aedd696f36430ea2a632506f2b1e3 (patch) | |
tree | 92593bd4554714e738387fb05a8d1dd883066bbf /src/video_core/engines/shader_bytecode.h | |
parent | shader_ir/conversion: Implement F2I F16 Ra.H1 (diff) | |
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Diffstat (limited to 'src/video_core/engines/shader_bytecode.h')
-rw-r--r-- | src/video_core/engines/shader_bytecode.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 35201c8be..747284700 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -1006,7 +1006,6 @@ union Instruction { } iset; union { - BitField<41, 2, u64> selector; BitField<45, 1, u64> negate_a; BitField<49, 1, u64> abs_a; BitField<10, 2, Register::Size> src_size; @@ -1031,6 +1030,14 @@ union Instruction { return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask); } } f2f; + + union { + BitField<41, 2, u64> selector; + } int_src; + + union { + BitField<41, 1, u64> selector; + } float_src; } conversion; union { |