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authorRodrigo Locatti <reinuseslisp@airmail.cc>2019-10-26 21:56:13 +0200
committerGitHub <noreply@github.com>2019-10-26 21:56:13 +0200
commit26f3e18c5cb882d48af702aa33519f4a2c74fa75 (patch)
treef17b70de1e1bca10e67a4f1076691a580f717f56 /src/video_core/engines
parentMerge pull request #3027 from lioncash/lookup (diff)
parentShader_IR: Address Feedback. (diff)
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Diffstat (limited to 'src/video_core/engines')
-rw-r--r--src/video_core/engines/const_buffer_engine_interface.h119
-rw-r--r--src/video_core/engines/kepler_compute.cpp20
-rw-r--r--src/video_core/engines/kepler_compute.h14
-rw-r--r--src/video_core/engines/maxwell_3d.cpp21
-rw-r--r--src/video_core/engines/maxwell_3d.h14
5 files changed, 182 insertions, 6 deletions
diff --git a/src/video_core/engines/const_buffer_engine_interface.h b/src/video_core/engines/const_buffer_engine_interface.h
new file mode 100644
index 000000000..ac27b6cbe
--- /dev/null
+++ b/src/video_core/engines/const_buffer_engine_interface.h
@@ -0,0 +1,119 @@
+// Copyright 2019 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <type_traits>
+#include "common/bit_field.h"
+#include "common/common_types.h"
+#include "video_core/engines/shader_bytecode.h"
+#include "video_core/textures/texture.h"
+
+namespace Tegra::Engines {
+
+enum class ShaderType : u32 {
+ Vertex = 0,
+ TesselationControl = 1,
+ TesselationEval = 2,
+ Geometry = 3,
+ Fragment = 4,
+ Compute = 5,
+};
+
+struct SamplerDescriptor {
+ union {
+ BitField<0, 20, Tegra::Shader::TextureType> texture_type;
+ BitField<20, 1, u32> is_array;
+ BitField<21, 1, u32> is_buffer;
+ BitField<22, 1, u32> is_shadow;
+ u32 raw{};
+ };
+
+ bool operator==(const SamplerDescriptor& rhs) const noexcept {
+ return raw == rhs.raw;
+ }
+
+ bool operator!=(const SamplerDescriptor& rhs) const noexcept {
+ return !operator==(rhs);
+ }
+
+ static SamplerDescriptor FromTicTexture(Tegra::Texture::TextureType tic_texture_type) {
+ SamplerDescriptor result;
+ switch (tic_texture_type) {
+ case Tegra::Texture::TextureType::Texture1D:
+ result.texture_type.Assign(Tegra::Shader::TextureType::Texture1D);
+ result.is_array.Assign(0);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ case Tegra::Texture::TextureType::Texture2D:
+ result.texture_type.Assign(Tegra::Shader::TextureType::Texture2D);
+ result.is_array.Assign(0);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ case Tegra::Texture::TextureType::Texture3D:
+ result.texture_type.Assign(Tegra::Shader::TextureType::Texture3D);
+ result.is_array.Assign(0);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ case Tegra::Texture::TextureType::TextureCubemap:
+ result.texture_type.Assign(Tegra::Shader::TextureType::TextureCube);
+ result.is_array.Assign(0);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ case Tegra::Texture::TextureType::Texture1DArray:
+ result.texture_type.Assign(Tegra::Shader::TextureType::Texture1D);
+ result.is_array.Assign(1);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ case Tegra::Texture::TextureType::Texture2DArray:
+ result.texture_type.Assign(Tegra::Shader::TextureType::Texture2D);
+ result.is_array.Assign(1);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ case Tegra::Texture::TextureType::Texture1DBuffer:
+ result.texture_type.Assign(Tegra::Shader::TextureType::Texture1D);
+ result.is_array.Assign(0);
+ result.is_buffer.Assign(1);
+ result.is_shadow.Assign(0);
+ return result;
+ case Tegra::Texture::TextureType::Texture2DNoMipmap:
+ result.texture_type.Assign(Tegra::Shader::TextureType::Texture2D);
+ result.is_array.Assign(0);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ case Tegra::Texture::TextureType::TextureCubeArray:
+ result.texture_type.Assign(Tegra::Shader::TextureType::TextureCube);
+ result.is_array.Assign(1);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ default:
+ result.texture_type.Assign(Tegra::Shader::TextureType::Texture2D);
+ result.is_array.Assign(0);
+ result.is_buffer.Assign(0);
+ result.is_shadow.Assign(0);
+ return result;
+ }
+ }
+};
+static_assert(std::is_trivially_copyable_v<SamplerDescriptor>);
+
+class ConstBufferEngineInterface {
+public:
+ virtual ~ConstBufferEngineInterface() = default;
+ virtual u32 AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const = 0;
+ virtual SamplerDescriptor AccessBoundSampler(ShaderType stage, u64 offset) const = 0;
+ virtual SamplerDescriptor AccessBindlessSampler(ShaderType stage, u64 const_buffer,
+ u64 offset) const = 0;
+ virtual u32 GetBoundBuffer() const = 0;
+};
+
+} // namespace Tegra::Engines
diff --git a/src/video_core/engines/kepler_compute.cpp b/src/video_core/engines/kepler_compute.cpp
index 63d449135..91adef360 100644
--- a/src/video_core/engines/kepler_compute.cpp
+++ b/src/video_core/engines/kepler_compute.cpp
@@ -70,13 +70,31 @@ Texture::FullTextureInfo KeplerCompute::GetTextureInfo(const Texture::TextureHan
GetTSCEntry(tex_handle.tsc_id)};
}
-u32 KeplerCompute::AccessConstBuffer32(u64 const_buffer, u64 offset) const {
+u32 KeplerCompute::AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const {
+ ASSERT(stage == ShaderType::Compute);
const auto& buffer = launch_description.const_buffer_config[const_buffer];
u32 result;
std::memcpy(&result, memory_manager.GetPointer(buffer.Address() + offset), sizeof(u32));
return result;
}
+SamplerDescriptor KeplerCompute::AccessBoundSampler(ShaderType stage, u64 offset) const {
+ return AccessBindlessSampler(stage, regs.tex_cb_index, offset * sizeof(Texture::TextureHandle));
+}
+
+SamplerDescriptor KeplerCompute::AccessBindlessSampler(ShaderType stage, u64 const_buffer,
+ u64 offset) const {
+ ASSERT(stage == ShaderType::Compute);
+ const auto& tex_info_buffer = launch_description.const_buffer_config[const_buffer];
+ const GPUVAddr tex_info_address = tex_info_buffer.Address() + offset;
+
+ const Texture::TextureHandle tex_handle{memory_manager.Read<u32>(tex_info_address)};
+ const Texture::FullTextureInfo tex_info = GetTextureInfo(tex_handle, offset);
+ SamplerDescriptor result = SamplerDescriptor::FromTicTexture(tex_info.tic.texture_type.Value());
+ result.is_shadow.Assign(tex_info.tsc.depth_compare_enabled.Value());
+ return result;
+}
+
void KeplerCompute::ProcessLaunch() {
const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
memory_manager.ReadBlockUnsafe(launch_desc_loc, &launch_description,
diff --git a/src/video_core/engines/kepler_compute.h b/src/video_core/engines/kepler_compute.h
index 90cf650d2..8e7182727 100644
--- a/src/video_core/engines/kepler_compute.h
+++ b/src/video_core/engines/kepler_compute.h
@@ -10,6 +10,7 @@
#include "common/bit_field.h"
#include "common/common_funcs.h"
#include "common/common_types.h"
+#include "video_core/engines/const_buffer_engine_interface.h"
#include "video_core/engines/engine_upload.h"
#include "video_core/gpu.h"
#include "video_core/textures/texture.h"
@@ -37,7 +38,7 @@ namespace Tegra::Engines {
#define KEPLER_COMPUTE_REG_INDEX(field_name) \
(offsetof(Tegra::Engines::KeplerCompute::Regs, field_name) / sizeof(u32))
-class KeplerCompute final {
+class KeplerCompute final : public ConstBufferEngineInterface {
public:
explicit KeplerCompute(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
MemoryManager& memory_manager);
@@ -201,7 +202,16 @@ public:
Texture::FullTextureInfo GetTextureInfo(const Texture::TextureHandle tex_handle,
std::size_t offset) const;
- u32 AccessConstBuffer32(u64 const_buffer, u64 offset) const;
+ u32 AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const override;
+
+ SamplerDescriptor AccessBoundSampler(ShaderType stage, u64 offset) const override;
+
+ SamplerDescriptor AccessBindlessSampler(ShaderType stage, u64 const_buffer,
+ u64 offset) const override;
+
+ u32 GetBoundBuffer() const override {
+ return regs.tex_cb_index;
+ }
private:
Core::System& system;
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 59976943a..558955451 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -847,7 +847,8 @@ void Maxwell3D::ProcessClearBuffers() {
rasterizer.Clear();
}
-u32 Maxwell3D::AccessConstBuffer32(Regs::ShaderStage stage, u64 const_buffer, u64 offset) const {
+u32 Maxwell3D::AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const {
+ ASSERT(stage != ShaderType::Compute);
const auto& shader_stage = state.shader_stages[static_cast<std::size_t>(stage)];
const auto& buffer = shader_stage.const_buffers[const_buffer];
u32 result;
@@ -855,4 +856,22 @@ u32 Maxwell3D::AccessConstBuffer32(Regs::ShaderStage stage, u64 const_buffer, u6
return result;
}
+SamplerDescriptor Maxwell3D::AccessBoundSampler(ShaderType stage, u64 offset) const {
+ return AccessBindlessSampler(stage, regs.tex_cb_index, offset * sizeof(Texture::TextureHandle));
+}
+
+SamplerDescriptor Maxwell3D::AccessBindlessSampler(ShaderType stage, u64 const_buffer,
+ u64 offset) const {
+ ASSERT(stage != ShaderType::Compute);
+ const auto& shader = state.shader_stages[static_cast<std::size_t>(stage)];
+ const auto& tex_info_buffer = shader.const_buffers[const_buffer];
+ const GPUVAddr tex_info_address = tex_info_buffer.address + offset;
+
+ const Texture::TextureHandle tex_handle{memory_manager.Read<u32>(tex_info_address)};
+ const Texture::FullTextureInfo tex_info = GetTextureInfo(tex_handle, offset);
+ SamplerDescriptor result = SamplerDescriptor::FromTicTexture(tex_info.tic.texture_type.Value());
+ result.is_shadow.Assign(tex_info.tsc.depth_compare_enabled.Value());
+ return result;
+}
+
} // namespace Tegra::Engines
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index e3f1047d5..fa846a621 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -15,6 +15,7 @@
#include "common/common_funcs.h"
#include "common/common_types.h"
#include "common/math_util.h"
+#include "video_core/engines/const_buffer_engine_interface.h"
#include "video_core/engines/const_buffer_info.h"
#include "video_core/engines/engine_upload.h"
#include "video_core/gpu.h"
@@ -44,7 +45,7 @@ namespace Tegra::Engines {
#define MAXWELL3D_REG_INDEX(field_name) \
(offsetof(Tegra::Engines::Maxwell3D::Regs, field_name) / sizeof(u32))
-class Maxwell3D final {
+class Maxwell3D final : public ConstBufferEngineInterface {
public:
explicit Maxwell3D(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
MemoryManager& memory_manager);
@@ -1257,7 +1258,16 @@ public:
/// Returns the texture information for a specific texture in a specific shader stage.
Texture::FullTextureInfo GetStageTexture(Regs::ShaderStage stage, std::size_t offset) const;
- u32 AccessConstBuffer32(Regs::ShaderStage stage, u64 const_buffer, u64 offset) const;
+ u32 AccessConstBuffer32(ShaderType stage, u64 const_buffer, u64 offset) const override;
+
+ SamplerDescriptor AccessBoundSampler(ShaderType stage, u64 offset) const override;
+
+ SamplerDescriptor AccessBindlessSampler(ShaderType stage, u64 const_buffer,
+ u64 offset) const override;
+
+ u32 GetBoundBuffer() const override {
+ return regs.tex_cb_index;
+ }
/// Memory for macro code - it's undetermined how big this is, however 1MB is much larger than
/// we've seen used.