summaryrefslogtreecommitdiffstats
path: root/src/video_core/shader/decode/arithmetic_integer_immediate.cpp
diff options
context:
space:
mode:
authorReinUsesLisp <reinuseslisp@airmail.cc>2019-01-30 06:09:40 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-02-03 21:21:20 +0100
commit42b75e8be8e468d90fa677e0c4026b32cf8c4636 (patch)
tree266aea8956258d62c2141959131c0f5ae73ac36e /src/video_core/shader/decode/arithmetic_integer_immediate.cpp
parentshader_ir: Pass decoded nodes as a whole instead of per basic blocks (diff)
downloadyuzu-42b75e8be8e468d90fa677e0c4026b32cf8c4636.tar
yuzu-42b75e8be8e468d90fa677e0c4026b32cf8c4636.tar.gz
yuzu-42b75e8be8e468d90fa677e0c4026b32cf8c4636.tar.bz2
yuzu-42b75e8be8e468d90fa677e0c4026b32cf8c4636.tar.lz
yuzu-42b75e8be8e468d90fa677e0c4026b32cf8c4636.tar.xz
yuzu-42b75e8be8e468d90fa677e0c4026b32cf8c4636.tar.zst
yuzu-42b75e8be8e468d90fa677e0c4026b32cf8c4636.zip
Diffstat (limited to 'src/video_core/shader/decode/arithmetic_integer_immediate.cpp')
-rw-r--r--src/video_core/shader/decode/arithmetic_integer_immediate.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer_immediate.cpp b/src/video_core/shader/decode/arithmetic_integer_immediate.cpp
index 3cbaeeaf5..3ed5ccc5a 100644
--- a/src/video_core/shader/decode/arithmetic_integer_immediate.cpp
+++ b/src/video_core/shader/decode/arithmetic_integer_immediate.cpp
@@ -16,7 +16,7 @@ using Tegra::Shader::Pred;
using Tegra::Shader::PredicateResultMode;
using Tegra::Shader::Register;
-u32 ShaderIR::DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc) {
+u32 ShaderIR::DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr);
@@ -54,9 +54,9 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc) {
return pc;
}
-void ShaderIR::WriteLogicOperation(BasicBlock& bb, Register dest, LogicOperation logic_op,
- Node op_a, Node op_b, PredicateResultMode predicate_mode,
- Pred predicate, bool sets_cc) {
+void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation logic_op, Node op_a,
+ Node op_b, PredicateResultMode predicate_mode, Pred predicate,
+ bool sets_cc) {
const Node result = [&]() {
switch (logic_op) {
case LogicOperation::And: