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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-23 05:33:47 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:52 +0100
commit027f443e699652fc30a849efaf8c12725a7b5729 (patch)
tree10f5c18227a20ce4cf9295107ee16e310e0d41da /src/video_core/shader/decode
parentshader_decode: Implement TLDS (untested) (diff)
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Diffstat (limited to 'src/video_core/shader/decode')
-rw-r--r--src/video_core/shader/decode/arithmetic_integer.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp
index b12dc5ba8..271ce205b 100644
--- a/src/video_core/shader/decode/arithmetic_integer.cpp
+++ b/src/video_core/shader/decode/arithmetic_integer.cpp
@@ -119,6 +119,16 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
SetRegister(bb, instr.gpr0, value);
break;
}
+ case OpCode::Id::POPC_C:
+ case OpCode::Id::POPC_R:
+ case OpCode::Id::POPC_IMM: {
+ if (instr.popc.invert) {
+ op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b);
+ }
+ const Node value = Operation(OperationCode::IBitCount, PRECISE, op_b);
+ SetRegister(bb, instr.gpr0, value);
+ break;
+ }
case OpCode::Id::SEL_C:
case OpCode::Id::SEL_R:
case OpCode::Id::SEL_IMM: {