summaryrefslogtreecommitdiffstats
path: root/src/video_core/shader/decode
diff options
context:
space:
mode:
authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-17 21:44:20 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:51 +0100
commitbecfdb863845d9ea81c1844c8ee3c681d03fd9ea (patch)
treee324530e67e44794791f50290a144dfd6f3fe184 /src/video_core/shader/decode
parentshader_decode: Implement LOP (diff)
downloadyuzu-becfdb863845d9ea81c1844c8ee3c681d03fd9ea.tar
yuzu-becfdb863845d9ea81c1844c8ee3c681d03fd9ea.tar.gz
yuzu-becfdb863845d9ea81c1844c8ee3c681d03fd9ea.tar.bz2
yuzu-becfdb863845d9ea81c1844c8ee3c681d03fd9ea.tar.lz
yuzu-becfdb863845d9ea81c1844c8ee3c681d03fd9ea.tar.xz
yuzu-becfdb863845d9ea81c1844c8ee3c681d03fd9ea.tar.zst
yuzu-becfdb863845d9ea81c1844c8ee3c681d03fd9ea.zip
Diffstat (limited to 'src/video_core/shader/decode')
-rw-r--r--src/video_core/shader/decode/other.cpp23
1 files changed, 22 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp
index ef0598d4f..0416d7eaa 100644
--- a/src/video_core/shader/decode/other.cpp
+++ b/src/video_core/shader/decode/other.cpp
@@ -64,7 +64,19 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
// The SSY opcode tells the GPU where to re-converge divergent execution paths, it sets the
// target of the jump that the SYNC instruction will make. The SSY opcode has a similar
// structure to the BRA opcode.
- bb.push_back(Operation(OperationCode::Ssy, Immediate(pc + instr.bra.GetBranchTarget())));
+ const u32 target = pc + instr.bra.GetBranchTarget();
+ bb.push_back(Operation(OperationCode::Ssy, Immediate(target)));
+ break;
+ }
+ case OpCode::Id::PBK: {
+ UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
+ "Constant buffer PBK is not supported");
+
+ // PBK pushes to a stack the address where BRK will jump to. This shares stack with SSY but
+ // using SYNC on a PBK address will kill the shader execution. We don't emulate this because
+ // it's very unlikely a driver will emit such invalid shader.
+ const u32 target = pc + instr.bra.GetBranchTarget();
+ bb.push_back(Operation(OperationCode::Pbk, Immediate(target)));
break;
}
case OpCode::Id::SYNC: {
@@ -76,6 +88,15 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
bb.push_back(Operation(OperationCode::Sync));
break;
}
+ case OpCode::Id::BRK: {
+ const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
+ UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "BRK condition code used: {}",
+ static_cast<u32>(cc));
+
+ // The BRK opcode jumps to the address previously set by the PBK opcode
+ bb.push_back(Operation(OperationCode::Brk));
+ break;
+ }
case OpCode::Id::IPA: {
const auto& attribute = instr.attribute.fmt28;
const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(),