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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-21 03:42:02 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:50 +0100
commitfbc67a05637f3acb47f933066fb2e548f9d35d8c (patch)
treef8e100455b0317dd29e4f97dd85506258ecc1978 /src/video_core
parentshader_ir: Add predicate combiner helper (diff)
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Diffstat (limited to 'src/video_core')
-rw-r--r--src/video_core/shader/shader_ir.cpp10
-rw-r--r--src/video_core/shader/shader_ir.h3
2 files changed, 13 insertions, 0 deletions
diff --git a/src/video_core/shader/shader_ir.cpp b/src/video_core/shader/shader_ir.cpp
index aec1fb36b..3c37c7145 100644
--- a/src/video_core/shader/shader_ir.cpp
+++ b/src/video_core/shader/shader_ir.cpp
@@ -321,6 +321,16 @@ OperationCode ShaderIR::GetPredicateCombiner(PredOperation operation) {
return op->second;
}
+Node ShaderIR::GetConditionCode(Tegra::Shader::ConditionCode cc) {
+ switch (cc) {
+ case Tegra::Shader::ConditionCode::NEU:
+ return GetInternalFlag(InternalFlag::Zero, true);
+ default:
+ UNIMPLEMENTED_MSG("Unimplemented condition code: {}", static_cast<u32>(cc));
+ return GetPredicate(static_cast<u64>(Pred::NeverExecute));
+ }
+}
+
void ShaderIR::SetRegister(BasicBlock& bb, Register dest, Node src) {
bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), src));
}
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h
index f13129ab3..8223ff044 100644
--- a/src/video_core/shader/shader_ir.h
+++ b/src/video_core/shader/shader_ir.h
@@ -672,6 +672,9 @@ private:
/// Returns a predicate combiner operation
OperationCode GetPredicateCombiner(Tegra::Shader::PredOperation operation);
+ /// Returns a condition code evaluated from internal flags
+ Node GetConditionCode(Tegra::Shader::ConditionCode cc);
+
template <typename... T>
inline Node Operation(OperationCode code, const T*... operands) {
return StoreNode(OperationNode(code, operands...));