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-rw-r--r--src/core/arm/arm_interface.cpp24
-rw-r--r--src/core/arm/arm_interface.h8
-rw-r--r--src/core/arm/cpu_interrupt_handler.h4
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.cpp10
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.h8
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp10
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.h8
-rw-r--r--src/core/arm/unicorn/arm_unicorn.cpp42
-rw-r--r--src/core/arm/unicorn/arm_unicorn.h8
9 files changed, 69 insertions, 53 deletions
diff --git a/src/core/arm/arm_interface.cpp b/src/core/arm/arm_interface.cpp
index d2295ed90..adc6aa5c5 100644
--- a/src/core/arm/arm_interface.cpp
+++ b/src/core/arm/arm_interface.cpp
@@ -147,10 +147,18 @@ std::vector<ARM_Interface::BacktraceEntry> ARM_Interface::GetBacktraceFromContex
auto fp = ctx.cpu_registers[29];
auto lr = ctx.cpu_registers[30];
while (true) {
- out.push_back({"", 0, lr, 0});
- if (!fp) {
+ out.push_back({
+ .module = "",
+ .address = 0,
+ .original_address = lr,
+ .offset = 0,
+ .name = "",
+ });
+
+ if (fp == 0) {
break;
}
+
lr = memory.Read64(fp + 8) - 4;
fp = memory.Read64(fp);
}
@@ -203,10 +211,18 @@ std::vector<ARM_Interface::BacktraceEntry> ARM_Interface::GetBacktrace() const {
auto fp = GetReg(29);
auto lr = GetReg(30);
while (true) {
- out.push_back({"", 0, lr, 0, ""});
- if (!fp) {
+ out.push_back({
+ .module = "",
+ .address = 0,
+ .original_address = lr,
+ .offset = 0,
+ .name = "",
+ });
+
+ if (fp == 0) {
break;
}
+
lr = memory.Read64(fp + 8) - 4;
fp = memory.Read64(fp);
}
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 1f24051e4..9b86247e2 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -93,14 +93,14 @@ public:
* @param index Register index
* @return Returns the value in the register
*/
- virtual u64 GetReg(int index) const = 0;
+ virtual u64 GetReg(std::size_t index) const = 0;
/**
* Set an ARM register
* @param index Register index
* @param value Value to set register to
*/
- virtual void SetReg(int index, u64 value) = 0;
+ virtual void SetReg(std::size_t index, u64 value) = 0;
/**
* Gets the value of a specified vector register.
@@ -108,7 +108,7 @@ public:
* @param index The index of the vector register.
* @return the value within the vector register.
*/
- virtual u128 GetVectorReg(int index) const = 0;
+ virtual u128 GetVectorReg(std::size_t index) const = 0;
/**
* Sets a given value into a vector register.
@@ -116,7 +116,7 @@ public:
* @param index The index of the vector register.
* @param value The new value to place in the register.
*/
- virtual void SetVectorReg(int index, u128 value) = 0;
+ virtual void SetVectorReg(std::size_t index, u128 value) = 0;
/**
* Get the current PSTATE register
diff --git a/src/core/arm/cpu_interrupt_handler.h b/src/core/arm/cpu_interrupt_handler.h
index 71e582f79..c20c280f1 100644
--- a/src/core/arm/cpu_interrupt_handler.h
+++ b/src/core/arm/cpu_interrupt_handler.h
@@ -21,8 +21,8 @@ public:
CPUInterruptHandler(const CPUInterruptHandler&) = delete;
CPUInterruptHandler& operator=(const CPUInterruptHandler&) = delete;
- CPUInterruptHandler(CPUInterruptHandler&&) = default;
- CPUInterruptHandler& operator=(CPUInterruptHandler&&) = default;
+ CPUInterruptHandler(CPUInterruptHandler&&) = delete;
+ CPUInterruptHandler& operator=(CPUInterruptHandler&&) = delete;
bool IsInterrupted() const {
return is_interrupted;
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
index b5f28a86e..fab694fc2 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
@@ -111,7 +111,7 @@ public:
}
return 0U;
}
- return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
+ return static_cast<u64>(std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0));
}
ARM_Dynarmic_32& parent;
@@ -210,19 +210,19 @@ u64 ARM_Dynarmic_32::GetPC() const {
return jit->Regs()[15];
}
-u64 ARM_Dynarmic_32::GetReg(int index) const {
+u64 ARM_Dynarmic_32::GetReg(std::size_t index) const {
return jit->Regs()[index];
}
-void ARM_Dynarmic_32::SetReg(int index, u64 value) {
+void ARM_Dynarmic_32::SetReg(std::size_t index, u64 value) {
jit->Regs()[index] = static_cast<u32>(value);
}
-u128 ARM_Dynarmic_32::GetVectorReg(int index) const {
+u128 ARM_Dynarmic_32::GetVectorReg(std::size_t index) const {
return {};
}
-void ARM_Dynarmic_32::SetVectorReg(int index, u128 value) {}
+void ARM_Dynarmic_32::SetVectorReg(std::size_t index, u128 value) {}
u32 ARM_Dynarmic_32::GetPSTATE() const {
return jit->Cpsr();
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.h b/src/core/arm/dynarmic/arm_dynarmic_32.h
index 2bab31b92..ba646c623 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.h
@@ -35,10 +35,10 @@ public:
void SetPC(u64 pc) override;
u64 GetPC() const override;
- u64 GetReg(int index) const override;
- void SetReg(int index, u64 value) override;
- u128 GetVectorReg(int index) const override;
- void SetVectorReg(int index, u128 value) override;
+ u64 GetReg(std::size_t index) const override;
+ void SetReg(std::size_t index, u64 value) override;
+ u128 GetVectorReg(std::size_t index) const override;
+ void SetVectorReg(std::size_t index, u128 value) override;
u32 GetPSTATE() const override;
void SetPSTATE(u32 pstate) override;
void Run() override;
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index ce9968724..a2c4c2f30 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -148,7 +148,7 @@ public:
}
return 0U;
}
- return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
+ return static_cast<u64>(std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0));
}
u64 GetCNTPCT() override {
@@ -265,19 +265,19 @@ u64 ARM_Dynarmic_64::GetPC() const {
return jit->GetPC();
}
-u64 ARM_Dynarmic_64::GetReg(int index) const {
+u64 ARM_Dynarmic_64::GetReg(std::size_t index) const {
return jit->GetRegister(index);
}
-void ARM_Dynarmic_64::SetReg(int index, u64 value) {
+void ARM_Dynarmic_64::SetReg(std::size_t index, u64 value) {
jit->SetRegister(index, value);
}
-u128 ARM_Dynarmic_64::GetVectorReg(int index) const {
+u128 ARM_Dynarmic_64::GetVectorReg(std::size_t index) const {
return jit->GetVector(index);
}
-void ARM_Dynarmic_64::SetVectorReg(int index, u128 value) {
+void ARM_Dynarmic_64::SetVectorReg(std::size_t index, u128 value) {
jit->SetVector(index, value);
}
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.h b/src/core/arm/dynarmic/arm_dynarmic_64.h
index 403c55961..2afb7e7a4 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.h
@@ -33,10 +33,10 @@ public:
void SetPC(u64 pc) override;
u64 GetPC() const override;
- u64 GetReg(int index) const override;
- void SetReg(int index, u64 value) override;
- u128 GetVectorReg(int index) const override;
- void SetVectorReg(int index, u128 value) override;
+ u64 GetReg(std::size_t index) const override;
+ void SetReg(std::size_t index, u64 value) override;
+ u128 GetVectorReg(std::size_t index) const override;
+ void SetVectorReg(std::size_t index, u128 value) override;
u32 GetPSTATE() const override;
void SetPSTATE(u32 pstate) override;
void Run() override;
diff --git a/src/core/arm/unicorn/arm_unicorn.cpp b/src/core/arm/unicorn/arm_unicorn.cpp
index 1df3f3ed1..c1612d626 100644
--- a/src/core/arm/unicorn/arm_unicorn.cpp
+++ b/src/core/arm/unicorn/arm_unicorn.cpp
@@ -96,35 +96,35 @@ u64 ARM_Unicorn::GetPC() const {
return val;
}
-u64 ARM_Unicorn::GetReg(int regn) const {
+u64 ARM_Unicorn::GetReg(std::size_t index) const {
u64 val{};
auto treg = UC_ARM64_REG_SP;
- if (regn <= 28) {
- treg = (uc_arm64_reg)(UC_ARM64_REG_X0 + regn);
- } else if (regn < 31) {
- treg = (uc_arm64_reg)(UC_ARM64_REG_X29 + regn - 29);
+ if (index <= 28) {
+ treg = static_cast<uc_arm64_reg>(UC_ARM64_REG_X0 + static_cast<int>(index));
+ } else if (index < 31) {
+ treg = static_cast<uc_arm64_reg>(UC_ARM64_REG_X29 + static_cast<int>(index) - 29);
}
CHECKED(uc_reg_read(uc, treg, &val));
return val;
}
-void ARM_Unicorn::SetReg(int regn, u64 val) {
+void ARM_Unicorn::SetReg(std::size_t index, u64 value) {
auto treg = UC_ARM64_REG_SP;
- if (regn <= 28) {
- treg = (uc_arm64_reg)(UC_ARM64_REG_X0 + regn);
- } else if (regn < 31) {
- treg = (uc_arm64_reg)(UC_ARM64_REG_X29 + regn - 29);
+ if (index <= 28) {
+ treg = static_cast<uc_arm64_reg>(UC_ARM64_REG_X0 + static_cast<int>(index));
+ } else if (index < 31) {
+ treg = static_cast<uc_arm64_reg>(UC_ARM64_REG_X29 + static_cast<int>(index) - 29);
}
- CHECKED(uc_reg_write(uc, treg, &val));
+ CHECKED(uc_reg_write(uc, treg, &value));
}
-u128 ARM_Unicorn::GetVectorReg(int /*index*/) const {
+u128 ARM_Unicorn::GetVectorReg(std::size_t /*index*/) const {
UNIMPLEMENTED();
static constexpr u128 res{};
return res;
}
-void ARM_Unicorn::SetVectorReg(int /*index*/, u128 /*value*/) {
+void ARM_Unicorn::SetVectorReg(std::size_t /*index*/, u128 /*value*/) {
UNIMPLEMENTED();
}
@@ -217,8 +217,8 @@ void ARM_Unicorn::SaveContext(ThreadContext64& ctx) {
CHECKED(uc_reg_read(uc, UC_ARM64_REG_PC, &ctx.pc));
CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &ctx.pstate));
- for (auto i = 0; i < 29; ++i) {
- uregs[i] = UC_ARM64_REG_X0 + i;
+ for (std::size_t i = 0; i < 29; ++i) {
+ uregs[i] = UC_ARM64_REG_X0 + static_cast<int>(i);
tregs[i] = &ctx.cpu_registers[i];
}
uregs[29] = UC_ARM64_REG_X29;
@@ -228,8 +228,8 @@ void ARM_Unicorn::SaveContext(ThreadContext64& ctx) {
CHECKED(uc_reg_read_batch(uc, uregs, tregs, 31));
- for (int i = 0; i < 32; ++i) {
- uregs[i] = UC_ARM64_REG_Q0 + i;
+ for (std::size_t i = 0; i < 32; ++i) {
+ uregs[i] = UC_ARM64_REG_Q0 + static_cast<int>(i);
tregs[i] = &ctx.vector_registers[i];
}
@@ -244,8 +244,8 @@ void ARM_Unicorn::LoadContext(const ThreadContext64& ctx) {
CHECKED(uc_reg_write(uc, UC_ARM64_REG_PC, &ctx.pc));
CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &ctx.pstate));
- for (int i = 0; i < 29; ++i) {
- uregs[i] = UC_ARM64_REG_X0 + i;
+ for (std::size_t i = 0; i < 29; ++i) {
+ uregs[i] = UC_ARM64_REG_X0 + static_cast<int>(i);
tregs[i] = (void*)&ctx.cpu_registers[i];
}
uregs[29] = UC_ARM64_REG_X29;
@@ -255,8 +255,8 @@ void ARM_Unicorn::LoadContext(const ThreadContext64& ctx) {
CHECKED(uc_reg_write_batch(uc, uregs, tregs, 31));
- for (auto i = 0; i < 32; ++i) {
- uregs[i] = UC_ARM64_REG_Q0 + i;
+ for (std::size_t i = 0; i < 32; ++i) {
+ uregs[i] = UC_ARM64_REG_Q0 + static_cast<int>(i);
tregs[i] = (void*)&ctx.vector_registers[i];
}
diff --git a/src/core/arm/unicorn/arm_unicorn.h b/src/core/arm/unicorn/arm_unicorn.h
index 810aff311..1183e9541 100644
--- a/src/core/arm/unicorn/arm_unicorn.h
+++ b/src/core/arm/unicorn/arm_unicorn.h
@@ -26,10 +26,10 @@ public:
void SetPC(u64 pc) override;
u64 GetPC() const override;
- u64 GetReg(int index) const override;
- void SetReg(int index, u64 value) override;
- u128 GetVectorReg(int index) const override;
- void SetVectorReg(int index, u128 value) override;
+ u64 GetReg(std::size_t index) const override;
+ void SetReg(std::size_t index, u64 value) override;
+ u128 GetVectorReg(std::size_t index) const override;
+ void SetVectorReg(std::size_t index, u128 value) override;
u32 GetPSTATE() const override;
void SetPSTATE(u32 pstate) override;
VAddr GetTlsAddress() const override;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 19:27:03 +0100