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* maxwell_3d: Add depth buffer enable, width, and height registers.bunnei2018-07-221-2/+14
* video_core: Use nested namespaces where applicableLioncash2018-07-216-28/+14
* maxwell_3d: Remove unused variable within GetStageTextures()Lioncash2018-07-201-2/+0
* GPU: Added register definitions for the stencil parameters.Subv2018-07-171-2/+25
* gl_rasterizer: Fix check for if a shader stage is enabled.bunnei2018-07-132-24/+8
* Merge pull request #655 from bunnei/pred-lt-nanbunnei2018-07-131-0/+1
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| * gl_shader_decompiler: Implement PredCondition::LessThanWithNan.bunnei2018-07-131-0/+1
* | gl_shader_decompiler: Use FlowCondition field in EXIT instruction.bunnei2018-07-131-0/+9
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* Merge pull request #652 from Subv/fadd32iSebastian Valle2018-07-131-0/+9
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| * GPU: Implement the FADD32I shader instruction.Subv2018-07-121-0/+9
* | Merge pull request #651 from Subv/ffma_decodebunnei2018-07-121-1/+1
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| * | GPU: Corrected the decoding of FFMA for immediate operands.Subv2018-07-121-1/+1
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* | Merge pull request #625 from Subv/imnmxbunnei2018-07-081-3/+17
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| * GPU: Implemented the IMNMX shader instruction.Subv2018-07-041-3/+17
* | Merge pull request #629 from Subv/depth_testbunnei2018-07-051-9/+21
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| * | GPU: Allow using the old NV04 values for the depth test function.Subv2018-07-051-9/+21
* | | Merge pull request #626 from Subv/shader_syncbunnei2018-07-051-0/+5
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| * | GPU: Stub the shader SYNC and DEPBAR instructions.Subv2018-07-041-0/+5
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* | Merge pull request #622 from Subv/unused_texbunnei2018-07-051-1/+1
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| * | GPU: Corrected the decoding for the TEX shader instruction.Subv2018-07-041-1/+1
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* | Merge pull request #621 from Subv/psetp_bunnei2018-07-051-0/+13
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| * | GPU: Implemented the PSETP shader instruction.Subv2018-07-041-0/+13
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* / GPU: Flip the triangle front face winding if the GPU is configured to not flip the triangles.Subv2018-07-041-3/+19
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* Merge pull request #609 from Subv/clear_buffersbunnei2018-07-042-2/+39
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| * GPU: Support clears that don't clear the color buffer.Subv2018-07-031-2/+3
| * GPU: Bind and clear the render target when the CLEAR_BUFFERS register is written to.Subv2018-07-031-0/+11
| * GPU: Added registers for the CLEAR_BUFFERS and CLEAR_COLOR methods.Subv2018-07-031-2/+27
* | Merge pull request #607 from jroweboy/loggingbunnei2018-07-033-5/+5
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| * | Update clang formatJames Rowe2018-07-032-3/+3
| * | Rename logging macro back to LOG_*James Rowe2018-07-033-3/+3
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* | Merge pull request #611 from Subv/enabled_depth_testbunnei2018-07-031-9/+9
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| * | GPU: Use only the least significant 3 bits when reading the depth test func.Subv2018-07-031-9/+9
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* | Merge pull request #610 from Subv/mufu_8bunnei2018-07-031-0/+1
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| * GPU: Implemented MUFU suboperation 8, sqrt.Subv2018-07-031-0/+1
* | Merge pull request #608 from Subv/depthbunnei2018-07-031-4/+52
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| * | GPU: Added registers for depth test and cull mode.Subv2018-07-021-3/+51
| * | GPU: Implemented the Z24S8 depth format and load the depth framebuffer.Subv2018-07-021-1/+1
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* | Merge pull request #606 from Subv/base_vertexSebastian Valle2018-07-021-1/+6
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| * | GPU: Added register definitions for the vertex buffer base element.Subv2018-07-021-1/+6
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* | Merge pull request #605 from Subv/dma_copySebastian Valle2018-07-021-1/+5
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| * GPU: Directly copy the pixels when performing a same-layout DMA.Subv2018-07-021-1/+5
* | Merge pull request #602 from Subv/mufu_subopbunnei2018-07-011-2/+1
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| * | GPU: Corrected the size of the MUFU subop field, and removed incorrect "min" operation.Subv2018-06-301-2/+1
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* / gl_shader_decompiler: Implement predicate NotEqualWithNan.bunnei2018-06-301-0/+1
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* maxwell_3d: Add a struct for RenderTargetConfig.bunnei2018-06-271-17/+19
* Build: Fixed some MSVC warnings in various parts of the code.Subv2018-06-202-4/+5
* GPU: Don't mark uniform buffers and registers as used for instructions which don't have them.Subv2018-06-191-2/+3
* gl_shader_decompiler: Implement LOP instructions.bunnei2018-06-171-0/+14
* gl_shader_decompiler: Refactor LOP32I instruction a bit in support of LOP.bunnei2018-06-171-3/+2
* gl_shader_decompiler: Implement integer size conversions for I2I/I2F/F2I.bunnei2018-06-161-1/+2
* Merge pull request #556 from Subv/dma_enginebunnei2018-06-123-0/+225
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| * GPU: Partially implemented the Maxwell DMA engine.Subv2018-06-123-0/+225
* | Merge pull request #558 from Subv/iadd32ibunnei2018-06-121-2/+10
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| * | GPU: Implemented the iadd32i shader instruction.Subv2018-06-121-2/+10
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* / gl_shader_decompiler: Implement saturate for float instructions.bunnei2018-06-121-2/+1
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* GPU: Implement the iset family of shader instructions.Subv2018-06-091-0/+9
* GPU: Added decodings for the ISET family of instructions.Subv2018-06-091-0/+7
* Merge pull request #550 from Subv/ssybunnei2018-06-091-0/+2
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| * GPU: Stub the SSY shader instruction.Subv2018-06-091-0/+2
* | Merge pull request #551 from bunnei/shrbunnei2018-06-091-0/+4
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| * | gl_shader_decompiler: Implement SHR instruction.bunnei2018-06-091-0/+4
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* | gl_shader_decompiler: Implement IADD instruction.bunnei2018-06-091-5/+11
* | gl_shader_decompiler: Add missing asserts for saturate_a instructions.bunnei2018-06-091-1/+1
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* GPU: Added registers for normal and independent blending.Subv2018-06-091-5/+26
* gl_shader_decompiler: Implement BFE_IMM instruction.bunnei2018-06-071-3/+15
* gl_shader_decompiler: F2F: Implement rounding modes.bunnei2018-06-071-3/+12
* shader_bytecode: Add instruction decodings for BFE, IMNMX, and XMAD.bunnei2018-06-071-0/+20
* Merge pull request #534 from Subv/multitexturingbunnei2018-06-072-0/+37
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| * GPU: Implement sampling multiple textures in the generated glsl shaders.Subv2018-06-062-0/+37
* | gl_shader_decompiler: Implement LD_C instruction.bunnei2018-06-071-0/+16
* | gl_shader_decompiler: Refactor uniform handling to allow different decodings.bunnei2018-06-061-6/+10
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* Merge pull request #516 from Subv/f2i_rbunnei2018-06-061-4/+20
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| * GPU: Implemented the F2I_R shader instruction.Subv2018-06-051-4/+20
* | Merge pull request #521 from Subv/brabunnei2018-06-051-4/+5
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| * | GPU: Corrected the branch targets for the shader bra instruction.Subv2018-06-051-4/+5
* | | gl_shader_decompiler: Implement SHL instruction.bunnei2018-06-051-13/+17
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* | GPU: Implement the ISCADD shader instructions.Subv2018-06-051-0/+16
* | GPU: Added decodings for the ISCADD instructions.Subv2018-06-051-0/+7
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* Merge pull request #514 from Subv/lop32ibunnei2018-06-051-1/+15
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| * GPU: Implemented the LOP32I instruction.Subv2018-06-041-1/+15
* | Merge pull request #510 from Subv/isetpbunnei2018-06-051-0/+10
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| * | GPU: Implemented the ISETP_R and ISETP_C shader instructions.Subv2018-06-041-0/+10
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* | Merge pull request #512 from Subv/fsetbunnei2018-06-051-1/+1
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| * | GPU: Use the bf bit in FSET to determine whether to write 0xFFFFFFFF or 1.0f.Subv2018-06-041-1/+1
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* | Merge pull request #501 from Subv/shader_brabunnei2018-06-051-0/+15
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| * | GPU: Partially implemented the shader BRA instruction.Subv2018-06-041-0/+13
| * | GPU: Added decoding for the BRA instruction.Subv2018-06-041-0/+2
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* / GPU: Calculate the correct viewport dimensions based on the scale and translate registers.Subv2018-06-041-12/+28
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* Merge pull request #500 from Subv/long_queriesbunnei2018-06-041-9/+24
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| * GPU: Partial implementation of long GPU queries.Subv2018-06-041-9/+24
* | gl_shader_decompiler: Implement TEXS component mask.bunnei2018-06-031-2/+16
* | Merge pull request #494 from bunnei/shader-texbunnei2018-06-031-0/+15
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| * | gl_shader_decompiler: Implement TEX instruction.bunnei2018-06-011-0/+10
| * | gl_shader_decompiler: Support multi-destination for TEXS.bunnei2018-06-011-0/+5
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* / gl_shader_decompiler: Implement RRO as a register move.bunnei2018-06-031-3/+7
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* Merge pull request #489 from Subv/vertexidbunnei2018-05-301-0/+4
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| * Shaders: Implemented reading the gl_InstanceID and gl_VertexID variables in the vertex shader.Subv2018-05-301-0/+4
* | gl_shader_decompiler: Partially implement F2F_R instruction.bunnei2018-05-301-3/+3
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* shader_bytecode: Implement other variants of FMNMX.bunnei2018-05-261-3/+7
* Merge pull request #458 from Subv/fmnmxbunnei2018-05-211-0/+5
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| * Shaders: Implemented the FMNMX shader instruction.Subv2018-05-211-0/+5
* | ShadersDecompiler: Added decoding for the PSETP instruction.Subv2018-05-191-0/+3
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* maxwell_3d: Reset vertex counts after drawing.bunnei2018-04-291-0/+10
* shader_bytecode: Add decoding for FMNMX instruction.bunnei2018-04-291-0/+2
* Merge pull request #416 from bunnei/shader-ints-p3bunnei2018-04-291-8/+25
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| * gl_shader_decompiler: Partially implement I2I_R, and I2F_R.bunnei2018-04-291-8/+8
| * shader_bytecode: Add decodings for i2i instructions.bunnei2018-04-291-3/+20
| * gl_shader_decompiler: Implement MOV32_IMM instruction.bunnei2018-04-291-2/+2
* | fermi_2d: Fix surface copy block height.bunnei2018-04-292-2/+7
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* general: Convert assertion macros over to be fmt-compatibleLioncash2018-04-271-2/+2
* gl_shader_decompiler: Boilerplate for handling integer instructions.bunnei2018-04-261-1/+9
* Merge pull request #396 from Subv/shader_opsbunnei2018-04-261-8/+35
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| * Shaders: Added bit decodings for the I2I instruction.Subv2018-04-251-0/+6
| * Shaders: Added decodings for the FSET instructions.Subv2018-04-251-8/+29
* | GPU: Partially implemented the Fermi2D surface copy operation.Subv2018-04-252-0/+59
* | GPU: Added surface copy registers to Fermi2DSubv2018-04-251-1/+57
* | GPU: Added boilerplate code for the Fermi2D engineSubv2018-04-252-2/+33
* | GPU: Reduce the number of registers of Maxwell3D to 0xE00.Subv2018-04-252-5/+5
* | GPU: Move the Maxwell3D macro uploading code to the inside of the Maxwell3D processor.Subv2018-04-252-8/+23
* | video-core: Move logging macros over to new fmt-capable onesLioncash2018-04-251-2/+2
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* memory_manager: Make GpuToCpuAddress return an optional.bunnei2018-04-241-10/+11
* memory_manager: Use GPUVAdddr, not PAddr, for GPU addresses.bunnei2018-04-241-6/+5
* Merge pull request #386 from Subv/gpu_querybunnei2018-04-242-2/+53
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| * GPU: Added asserts to our code for handling the QUERY_GET GPU command.Subv2018-04-242-2/+53
* | GPU: Support multiple enabled vertex arrays.Subv2018-04-231-0/+5
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* shader_bytecode: Add several more instruction decodings.bunnei2018-04-211-5/+52
* shader_bytecode: Decode instructions based on bit strings.bunnei2018-04-211-185/+172
* ShaderGen: Implemented predicated instruction execution.Subv2018-04-211-1/+5
* ShaderGen: Implemented the fsetp instruction.Subv2018-04-211-3/+40
* ShaderGen: Register id 255 is special and is hardcoded to return 0 (SR_ZERO).Subv2018-04-201-0/+3
* ShaderGen: Implemented the fmul32i shader instruction.Subv2018-04-191-3/+14
* gl_shader_gen: Support vertical/horizontal viewport flipping. (#347)bunnei2018-04-181-1/+10
* GPU: Pitch textures are now supported, don't assert when encountering them.Subv2018-04-181-2/+3
* Merge pull request #346 from bunnei/misc-gpu-improvementsbunnei2018-04-181-1/+2
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| * maxwell3d: Allow Texture2DNoMipmap as Texture2D.bunnei2018-04-181-1/+2
* | Merge pull request #344 from bunnei/shader-decompiler-p2bunnei2018-04-181-10/+33
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| * | shader_bytecode: Make ctor's constexpr and explicit.bunnei2018-04-181-7/+7
| * | gl_shader_decompiler: Implement FMUL/FADD/FFMA immediate instructions.bunnei2018-04-171-0/+14
| * | gl_shader_decompiler: Add support for TEXS instruction.bunnei2018-04-171-5/+14
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* / renderer_opengl: Implement BlendEquation and BlendFunc.bunnei2018-04-182-4/+48
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* gl_rasterizer: Implement indexed vertex mode.bunnei2018-04-172-2/+46
* GPU: Added a function to determine whether a shader stage is enabled or not.Subv2018-04-152-0/+24
* shaders: Add NumTextureSamplers const, remove unused #pragma.bunnei2018-04-151-2/+0
* shaders: Address PR review feedback.bunnei2018-04-141-1/+1
* shaders: Fix GCC and clang build issues.bunnei2018-04-141-3/+3
* gl_shader_decompiler: Implement negate, abs, etc. and lots of cleanup.bunnei2018-04-141-20/+39
* shader_bytecode: Add FSETP and KIL to GetInfo.bunnei2018-04-141-0/+3
* shader_bytecode: Add SubOp decoding.bunnei2018-04-141-0/+10
* maxwell_3d: Make memory_manager public.bunnei2018-04-141-2/+1
* maxwell_3d: Fix shader_config decodings.bunnei2018-04-141-6/+3
* shader_bytecode: Add initial module for shader decoding.bunnei2018-04-141-0/+297
* GPU: Assert when finding a texture with a format type other than UNORM.Subv2018-04-071-0/+2
* GPU: Use the MacroInterpreter class to execute the GPU macros instead of HLEing them.Subv2018-04-012-121/+13
* GPU: Implemented a gpu macro interpreter.Subv2018-04-012-0/+8
* gl_rasterizer: Add a SyncViewport method.bunnei2018-03-271-0/+10
* gl_rasterizer: Normalize vertex array data as appropriate.bunnei2018-03-271-0/+4
* maxwell_3d: Use names that match envytools for VertexType.bunnei2018-03-271-8/+8
* maxwell_3d: Add VertexAttribute struct and cleanup.bunnei2018-03-271-121/+160
* Maxwell3D: Call AccelerateDrawBatch on DrawArrays.bunnei2018-03-271-1/+8
* gl_rasterizer: Implement AnalyzeVertexArray.bunnei2018-03-271-0/+35
* maxwell: Add RenderTargetFormat enum.bunnei2018-03-271-3/+4
* GPU: Load the sampler info (TSC) when retrieving active textures.Subv2018-03-262-21/+67
* GPU: Make the debug_context variable a member of the frontend instead of a global.Subv2018-03-251-11/+13
* GPU: Added a function to retrieve the active textures for a shader stage.Subv2018-03-242-50/+59
* GPU: Implement the Incoming/FinishedPrimitiveBatch debug breakpoints.Subv2018-03-241-0/+7
* GPU: Implement the MaxwellCommandLoaded/Processed debug breakpoints.Subv2018-03-241-0/+10
* GPU: Added a method to unswizzle a texture without decoding it.Subv2018-03-241-1/+1
* GPU: Preliminary work for texture decoding.Subv2018-03-241-0/+45
* GPU: Added viewport registers to Maxwell3D's reg structure.Subv2018-03-241-1/+18
* maxwell_3d: Add some format decodings and string helper functions.bunnei2018-03-231-3/+107
* GPU: Added vertex attribute format registers.Subv2018-03-211-1/+14
* GPU: Added registers for the number of vertices to render.Subv2018-03-211-2/+13
* Merge pull request #253 from Subv/rt_depthMat M2018-03-201-1/+48
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| * GPU: Added Z buffer registers to Maxwell3D's reg structure.Subv2018-03-191-1/+17
| * GPU: Added the render target (RT) registers to Maxwell3D's reg structure.Subv2018-03-191-1/+32
* | Clang FixesN00byKing2018-03-191-1/+2
* | Clean Warnings (?)N00byKing2018-03-191-1/+1
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* GPU: Added the TSC registers to the Maxwell3D register structure.Subv2018-03-191-1/+15
* GPU: Added the TIC registers to the Maxwell3D register structure.Subv2018-03-191-1/+16
* GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE.Subv2018-03-192-1/+29
* GPU: Implement the BindStorageBuffer macro method in HLE.Subv2018-03-182-1/+36
* GPU: Handle writes to the CB_DATA method.Subv2018-03-182-0/+39
* GPU: Store uploaded GPU macros and keep track of the number of method parameters.Subv2018-03-182-11/+24
* GPU: Macros are specific to the Maxwell3D engine, so handle them internally.Subv2018-03-186-31/+55
* GPU: Renamed ShaderType to ShaderStage as that is less confusing.Subv2018-03-182-19/+19
* GPU: Store shader constbuffer bindings in the GPU state.Subv2018-03-182-5/+61
* GPU: Corrected some register offsets and removed superfluous macro registers.Subv2018-03-181-9/+3
* GPU: Make the SetShader macro call do the same as the real macro's code.Subv2018-03-182-3/+44
* GPU: Corrected the parameter documentation for the SetShader macro call.Subv2018-03-172-11/+12
* Merge pull request #242 from Subv/set_shaderbunnei2018-03-172-4/+38
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| * GPU: Handle the SetShader method call (0xE24) and store the shader config.Subv2018-03-172-4/+38
* | GPU: Added the vertex array registers.Subv2018-03-171-2/+33
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* Merge pull request #241 from Subv/gpu_method_callbunnei2018-03-176-1/+56
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| * GPU: Process command mode 5 (IncreaseOnce) differently from other commands.Subv2018-03-176-1/+56
* | GPU: Assert that we get a 0 CODE_ADDRESS register in the 3D engine.Subv2018-03-171-0/+8
* | GPU: Added Maxwell registers for Shader Program control.Subv2018-03-171-2/+55
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* GPU: Intercept writes to the VERTEX_END_GL register.Subv2018-03-052-1/+18
* maxwell_3d: Make constructor explicitLioncash2018-02-141-1/+1
* GPU: Partially implemented the QUERY_* registers in the Maxwell3D engine.Subv2018-02-122-2/+94
* Make a GPU class in VideoCore to contain the GPU state.Subv2018-02-126-18/+24
* GPU: Added a command processor to decode the GPU pushbuffers and forward the commands to their respective engines.Subv2018-02-126-0/+99
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