summaryrefslogtreecommitdiffstats
path: root/src/core/arm/skyeye_common/armmmu.h
blob: 30858f9ba9951641e1ab1aa17abf7d88f3c1aefa (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
/*
    armmmu.c - Memory Management Unit emulation.
    ARMulator extensions for the ARM7100 family.
    Copyright (C) 1999  Ben Williamson

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

#ifndef _ARMMMU_H_
#define _ARMMMU_H_


#define WORD_SHT			2
#define WORD_SIZE			(1<<WORD_SHT)
/* The MMU is accessible with MCR and MRC operations to copro 15: */

#define MMU_COPRO			(15)

/* Register numbers in the MMU: */

typedef enum mmu_regnum_t
{
	MMU_ID = 0,
	MMU_CONTROL = 1,
	MMU_TRANSLATION_TABLE_BASE = 2,
	MMU_DOMAIN_ACCESS_CONTROL = 3,
	MMU_FAULT_STATUS = 5,
	MMU_FAULT_ADDRESS = 6,
	MMU_CACHE_OPS = 7,
	MMU_TLB_OPS = 8,
	MMU_CACHE_LOCKDOWN = 9,
	MMU_TLB_LOCKDOWN = 10,
	MMU_PID = 13,

	/*MMU_V4 */
	MMU_V4_CACHE_OPS = 7,
	MMU_V4_TLB_OPS = 8,

	/*MMU_V3 */
	MMU_V3_FLUSH_TLB = 5,
	MMU_V3_FLUSH_TLB_ENTRY = 6,
	MMU_V3_FLUSH_CACHE = 7,

	/*MMU Intel SA-1100 */
	MMU_SA_RB_OPS = 9,
	MMU_SA_DEBUG = 14,
	MMU_SA_CP15_R15 = 15,
	//chy 2003-08-24
	/*Intel xscale CP15 */
	XSCALE_CP15_CACHE_TYPE = 0,
	XSCALE_CP15_AUX_CONTROL = 1,
	XSCALE_CP15_COPRO_ACCESS = 15,

} mmu_regnum_t;

/* Bits in the control register */

#define CONTROL_MMU			(1<<0)
#define CONTROL_ALIGN_FAULT		(1<<1)
#define CONTROL_CACHE			(1<<2)
#define CONTROL_DATA_CACHE		(1<<2)
#define CONTROL_WRITE_BUFFER		(1<<3)
#define CONTROL_BIG_ENDIAN		(1<<7)
#define CONTROL_SYSTEM			(1<<8)
#define CONTROL_ROM			(1<<9)
#define CONTROL_UNDEFINED               (1<<10)
#define CONTROL_BRANCH_PREDICT          (1<<11)
#define CONTROL_INSTRUCTION_CACHE       (1<<12)
#define CONTROL_VECTOR                  (1<<13)
#define CONTROL_RR                      (1<<14)
#define CONTROL_L4                      (1<<15)
#define CONTROL_XP                      (1<<23)
#define CONTROL_EE                      (1<<25)

/*Macro defines for MMU state*/
#define MMU_CTL (state->mmu.control)
#define MMU_Enabled (state->mmu.control & CONTROL_MMU)
#define MMU_Disabled (!(MMU_Enabled))
#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT)

#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE)
#define MMU_ICacheDisabled (!(MMU_ICacheDisabled))

#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE)
#define MMU_DCacheDisabled (!(MMU_DCacheEnabled))

#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE)
#define MMU_CacheDisabled (!(MMU_CacheEnabled))

#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER)
#define MMU_WBDisabled (!(MMU_WBEnabled))

/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
#define PID_VA_MAP_MASK	0xfe000000
//#define mmu_pid_va_map(va) ({\
//	ARMword ret; \
//	if ((va) & PID_VA_MAP_MASK)\
//		ret = (va); \
//	else \
//		ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
//	ret;\
//})
#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))

/* FS[3:0] in the fault status register: */

typedef enum fault_t
{
	NO_FAULT = 0x0,
	ALIGNMENT_FAULT = 0x1,

	SECTION_TRANSLATION_FAULT = 0x5,
	PAGE_TRANSLATION_FAULT = 0x7,
	SECTION_DOMAIN_FAULT = 0x9,
	PAGE_DOMAIN_FAULT = 0xB,
	SECTION_PERMISSION_FAULT = 0xD,
	SUBPAGE_PERMISSION_FAULT = 0xF,

	/* defined by skyeye */
	TLB_READ_MISS = 0x30,
	TLB_WRITE_MISS = 0x40,

} fault_t;

#endif /* _ARMMMU_H_ */