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* GPU: Added the TSC registers to the Maxwell3D register structure.Subv2018-03-191-1/+15
* GPU: Added the TIC registers to the Maxwell3D register structure.Subv2018-03-191-1/+16
* GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE.Subv2018-03-192-1/+29
* GPU: Implement the BindStorageBuffer macro method in HLE.Subv2018-03-182-1/+36
* GPU: Handle writes to the CB_DATA method.Subv2018-03-182-0/+39
* GPU: Store uploaded GPU macros and keep track of the number of method parameters.Subv2018-03-182-11/+24
* GPU: Macros are specific to the Maxwell3D engine, so handle them internally.Subv2018-03-186-31/+55
* GPU: Renamed ShaderType to ShaderStage as that is less confusing.Subv2018-03-182-19/+19
* GPU: Store shader constbuffer bindings in the GPU state.Subv2018-03-182-5/+61
* GPU: Corrected some register offsets and removed superfluous macro registers.Subv2018-03-181-9/+3
* GPU: Make the SetShader macro call do the same as the real macro's code.Subv2018-03-182-3/+44
* GPU: Corrected the parameter documentation for the SetShader macro call.Subv2018-03-172-11/+12
* Merge pull request #242 from Subv/set_shaderbunnei2018-03-172-4/+38
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| * GPU: Handle the SetShader method call (0xE24) and store the shader config.Subv2018-03-172-4/+38
* | GPU: Added the vertex array registers.Subv2018-03-171-2/+33
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* Merge pull request #241 from Subv/gpu_method_callbunnei2018-03-176-1/+56
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| * GPU: Process command mode 5 (IncreaseOnce) differently from other commands.Subv2018-03-176-1/+56
* | GPU: Assert that we get a 0 CODE_ADDRESS register in the 3D engine.Subv2018-03-171-0/+8
* | GPU: Added Maxwell registers for Shader Program control.Subv2018-03-171-2/+55
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* GPU: Intercept writes to the VERTEX_END_GL register.Subv2018-03-052-1/+18
* maxwell_3d: Make constructor explicitLioncash2018-02-141-1/+1
* GPU: Partially implemented the QUERY_* registers in the Maxwell3D engine.Subv2018-02-122-2/+94
* Make a GPU class in VideoCore to contain the GPU state.Subv2018-02-126-18/+24
* GPU: Added a command processor to decode the GPU pushbuffers and forward the commands to their respective engines.Subv2018-02-126-0/+99